Data recording medium, data recording method and device, and encode method and device

ABSTRACT

A recording method for converting m-bit data into n-bit (where n&gt;m) data whose run length is restricted and recording the converted data on a recording medium, the recording method comprising the step of selecting first n-bit data according to an immediately preceded n-bit data, first n-bit data immediately followed thereby, and second n-bit data immediately followed thereby so that the cumulative value of DC components per unit time becomes small.

TECHNICAL FIELD

The present invention relates to a data recording medium, a datarecording method, a data recording apparatus, an encoding method, and anencoding apparatus that are applicable to for example an optical disc.

BACKGROUND ART

Since optical discs such as a CD (Compact Disc) and a CD-ROM (CompactDisc Read Only Memory) are easy to handle and are produced at relativelylow cost, they have been widely used as recording mediums for storingdata. In recent years, a CD-R (Compact Disc Recordable) disc, on whichdata can be recorded once, and a CD-RW (Compact Disc ReWritable) disc,on which data can be rewritten, have come out. Thus, data can be easilyrecorded on such recordable optical discs. As a result, optical discsthat accord with the CD standard such as a CD-DA (Compact Disc DigitalAudio) disc, a CD-ROM disc, a CD-R disc, and a CD-RW disc have becomethe mainstream of data recording mediums. In addition, in recent years,audio data is compressed according to the MP3 (MPEG1 Audio Layer-3) andthe ATRAC (Adaptive TRansform Acoustic Coding) 3 and recorded on theCD-R disc, the CD-RW disc, and so forth.

However, as a CD-R disc and a CD-RW disc have come out, data recoded ona CD disc can be easily copied to these discs. As a result, a problemabout copyright protection has arisen. Thus, when content data isrecorded to a CD disc, it is necessary to take measures to protectcontent data.

As a conventional copy protection technology for protecting a copy ofdata from a CD-ROM disc to a CD-R disc or a CD-RW disc, a method forphysically deforming a disc with for example wobble pits has beenproposed. In the physically deforming method, however, if an originaldisc is a CD-R disc or a CD-RW disc, the copy protection cannot beperformed.

In addition, to protect a copying operation, a method for encryptingcontent data has been proposed. However, even if content data has beenencrypted, a disc on which the same data as an original disc is recordedcan be produced.

To protect content data recorded on a CD disc that accords with the CDstandard, there is a method for determining whether the disc is anoriginal CD or a CD whose data has been copied from an original CD (thisCD is referred to as copied CD). When the disc is an original CD, acopying operation thereof can be permitted. When the disc is a discwhose data has been copied from an original disc (this disc is referredto as copied disc), a further copying operation thereof can beprohibited.

To determine whether the disc is an original disc or a copied disc, amethod for placing a defect on a disc in a master disc production stage,detecting the defect from the disc during a reproduction, anddetermining that the disc is an original disc based on the detecteddefect has been proposed. In this method, however, an original disc maycontain such a defect. In addition, depending on the type of a defect,it may be copied as it is. Thus, content data of an original disc cannotbe prevented from being copied to a CD-R disc.

Therefore, an object of the present invention is to provide a datarecording medium, a data recording method, and a data recordingapparatus that contribute to copy protection without need to physicallydeform a medium and intentionally place a defect thereon.

DISCLOSURE OF THE INVENTION

Claim 1 of the present invention is a recording method for convertingm-bit data into an n-bit (where n>m) data symbol whose run length isrestricted and placing a connection bit after the m-bit data symbol sothat the cumulative value of DC components per unit time becomes small,the recording method comprising the steps of selecting a firstconnection bit to be added to an immediately preceded data symbol from aplurality of connection bits according to at least one first connectionbit that can be added between the immediately preceded data symbol and afirst data symbol immediately followed thereby and according to at leastone second connection bit that can be added between the first datasymbol and at least one second data symbol immediately followed thereby;adding the selected first connection bit to the immediately precededdata symbol so as to generate record data; and recording the generatedrecord data on a recording medium.

Claim 4 of the present invention is a recording method for convertingm-bit data into an n-bit (where n>m) data symbol whose run,length isrestricted and adding a connection bit after the m-bit data symbol sothat the cumulative value of DC components per unit time becomes small,the recording method comprising the steps of when an immediatelypreceded data symbol is a special data symbol, selecting a firstconnection bit to be added to the immediately preceded data symbol froma plurality of connection bits according to at least one firstconnection bit that can be added between the immediately preceded datasymbol and a first data symbol immediately followed thereby andaccording to at least one second connection bit that can be addedbetween the first data symbol and at least one second data symbolimmediately followed thereby; adding the selected first connection bitto the immediately preceded data symbol so as to generate record data;and recording the generated record data on a recording medium.

Claim 9 of the present invention is a recording method for convertingm-bit data into n-bit (where n>m) data whose run length is restrictedand recording the converted data on a recording medium, the recordingmethod comprising the step of selecting first n-bit data according to animmediately preceded n-bit data, first n-bit data immediately followedthereby, and second n-bit data immediately followed thereby so that thecumulative value of DC components per unit time becomes small.

Claim 19 of the present invention is a recording apparatus, comprisingan encoding process portion for performing an encoding process for inputdata; a converting portion for converting m-bit data that is output fromthe encoding processing portion into n-bit (where n>m) data whose runlength is restricted by selecting first n-bit data according to animmediately preceded n-bit data, first n-bit data immediately followedthereby, and second n-bit data immediately followed thereby so that thecumulative value of DC components per unit time becomes small; and arecording portion for recording data that is output from the convertingportion on a recording medium.

Claim 29 of the present invention is a recording medium on which whenm-bit data is converted into n-bit (where n>m) data whose run length isrestricted, first n-bit data is selected according to an immediatelypreceded n-bit data, first n-bit data immediately followed thereby, andsecond n-bit data immediately followed thereby so that the cumulativevalue of DC components per unit time becomes small and the selectedfirst n-bit data is recorded after the immediately preceded n-bit data.

Claim 39 of the present invention is a data converting method,comprising the step of when m-bit data is converted into n-bit (wheren>m) data whose run length is restricted, selecting first n-bit dataaccording to an immediately preceded n-bit data, first n-bit dataimmediately followed thereby, and second n-bit data immediately followedthereby so that the cumulative value of DC components per unit timebecomes small.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an example of the structure of amastering apparatus according to an embodiment of the present invention.

FIG. 2A and FIG. 2B are schematic diagrams showing an example of aspecial pattern recorded on a disc.

FIG. 3 is a schematic diagram describing the format of an EFM frame of aCD.

FIG. 4 is a schematic diagram describing a sub code block of a CD.

FIG. 5 is a schematic diagram describing Q channel of a sub code.

FIG. 6A and FIG. 6B are schematic diagrams describing data of a subcode.

FIG. 7 is a schematic diagram showing an EFM conversion table.

FIG. 8 is a schematic diagram showing an EFM conversion table.

FIG. 9 is a schematic diagram showing an EFM conversion table.

FIG. 10 is a schematic diagram showing an EFM conversion table.

FIG. 11 is a schematic diagram showing an EFM conversion table.

FIG. 12 is a schematic diagram showing an EFM conversion table.

FIG. 13A to FIG. 13D are schematic diagrams describing a method forselecting merging bits.

FIG. 14A, FIG. 14B, and FIG. 14C are schematic diagrams showing anexample of a special pattern of which DSV does not converge.

FIG. 15A, FIG. 15B, and FIG. 15C are schematic diagrams showing anotherexample of a special pattern of which DSV does not converge.

FIG. 16A, FIG. 16B, and FIG. 16C are schematic diagrams showing afurther example of a special pattern of which DSV does not converge.

FIG. 17A to FIG. 17E are schematic diagrams showing an example of aspecial pattern of which DSV does not converge in the EFM modulationwhen DSV is controlled according to only the relation of an immediatelypreceded code symbol and a code symbol immediately followed thereby.

FIG. 18 is a schematic diagram describing an example of a specialpattern of which DSV does not converge in the EFM modulation when DSV iscontrolled according to only the relation of an immediately precededcode symbol and a code symbol immediately followed thereby.

FIG. 19 is a flow chart describing a merging bit selecting processperformed by a modulator according to the present invention.

FIG. 20A and FIG. 20B are schematic diagrams describing the merging bitselecting process performed by the modulator according to the presentinvention.

FIG. 21 is a block diagram showing an example of a CD reproducingapparatus.

FIG. 22 is a flow chart describing a merging bit selecting processperformed by a conventional modulator.

FIG. 23A and FIG. 23B are schematic diagrams describing the merging bitselecting process performed by the conventional modulator.

FIG. 24 is a block diagram describing a flow of a disc copying process.

FIG. 25 is a block diagram showing an outline of a reproducing processportion when a disc copying process is performed.

FIG. 26 is a block diagram showing an outline of a recording processportion when a disc copying process is performed.

BEST MODES FOR CARRYING OUT THE INVENTION

Next, with reference to the accompanying drawings, an embodiment of thepresent invention will be described. In this example, copy restrictionis performed with a special pattern of which when connection bits(hereinafter referred to as merging bits) are selected in the EFM (eightto fourteen modulation) modulation, the merging bits selected when DSV(Digital Sum Variation) is controlled according to the relation of animmediately preceded code symbol and a code symbol immediately followedthereby are different from the merging bits selected in the EFMmodulation when DSV is controlled according to the relation of that codesymbol and a code symbol further immediately followed thereby.

FIG. 1 shows an example of the structure of a mastering apparatus thatproduces a data recording medium according to the present invention. Adata recording medium is for example an optical disc that accords withfor example the CD (Compact Disc) standard. The mastering apparatus hasa laser light source 1 that is a gas laser (for example, an Ar ionlaser, an He-Cd laser, or a Kr ion laser) or a semiconductor laser, anacoustooptic effect type or electrooptic type optical modulator 2 thatmodulates laser light emitted from the laser light source 1, and anoptical pickup 3 that has an objective lens that collects laser lightthat has passed through the optical modulator 2 and radiates thecollected light to a photoresist surface of a disc shaped glass masterdisc 4 on which photoresist as a photosensitive material has beencoated.

The optical modulator 2 modulates the laser light emitted from the laserlight source 1 corresponding to a supplied record signal. The masteringapparatus radiates the modulated laser light to the glass master disc 4.As a result, a master on which data has been recorded is produced. Inaddition, the mastering apparatus has a servo portion (not shown). Theservo portion performs a tracking control for controlling the relativepositions of the optical pickup 3 and the master disc 4 and a rotationdriving operation control of a spindle motor 5. The rotations of theglass master disc 4 are driven by the spindle motor 5 at for exampleconstant linear velocity.

The record signal is supplied from an EFM modulator 12 to the opticalmodulator 2. Main digital data to be recorded is supplied from an inputterminal 6. The main digital data is for example two-channel stereodigital audio data. Of course, the main digital data may be stillpicture data, video data, or CD-ROM data as well as digital audio data.The main digital data may be also digital audio data that has beencompressed according to the MP3, the ATRAC, or the like. To protectdata, the main digital data may be encrypted data.

A sub code of channels P to W according to the current CD standard issupplied from an input terminal 7. A frame sync is supplied to an inputterminal 9.

In addition, special pattern data is supplied from an input terminal 8.In the special pattern, merging bits selected in the EFM modulation whenDSV is controlled according to the relation of an immediately precededcode symbol and a code immediately followed thereby are different frommerging bits selected in the EFM modulation when DSV is controlledaccording to the relation of that code symbol and a code symbol furtherimmediately followed thereby. In reality, as shown in FIG. 2A and FIG.2B, a special pattern is a pattern of which sub code data “00h (where hrepresents hexadecimal notation)” or “40h” is followed by a data symbol“90h”, followed by data symbols “B9h” and “9Ah” that are alternatelyrepeated in one frame. When the sub code data “00h” and “40h” areconverted according to an EFM table, code symbols (01001000100000) and(01001000100100) are obtained, respectively. The low order two bits ofthese code symbols are (00), which is 2T or more. The EFM conversiontable will be described later. It should be noted that the foregoingpattern is just an example.

The main digital data supplied from the input terminal 6 and the specialpattern data supplied from the input terminal 8 are supplied to a CIRC(Cross Interleave Reed-Solomon Code) encoder 17 through a switch circuit11. The switch circuit 11 is switched at a predetermined timingaccording to an output of an area controlling circuit 16 so as to placedata of the special pattern at a predetermined position of the maindigital data. The CIRC encoder 17 performs an error correction codeencoding process for adding error correction parity data or the like anda scrambling process. In other words, 16 bits of one sample or one wordare divided into two symbols that are high order eight bits and loworder eight bits. In the unit of one symbol, the error correction codeencoding process for adding for example CIRC error correction paritydata or the like and the scrambling process are performed.

The sub code data supplied from the input terminal 7 is converted intosub code data having the EFM frame format of a sub code by a sub codeencoder 10.

An output of the CIRC encoder 17 and an output of the sub code encoder10 are supplied to a multiplexer 13. The multiplexer 13 arranges datathat is output from the CIRC encoder 17 and the sub code encoder 10 in apredetermined order. Output data of the multiplexer 13 is supplied tothe EFM modulator 12. The EFM modulator 12 converts a symbol of eightbits into data of 14 channel bits according to the conversion table. Aframe sync is supplied to the EFM modulator 12.

In association with the EFM modulator 12, a merging bit selectingportion 14 and a DSV controlling portion 15 are disposed. The mergingbit selecting portion 14 and the DSV controlling portion 15 selectmerging bits (000), (001), (010), or (100) that satisfies the run lengthlimit conditions (Tmin=3T and Tmax=11T) and of which DSV approaches to“0”. The merging bit selecting portion 14 and the DSV controllingportion 15 perform a merging bit selecting process according to not onlythe relation of an immediately preceded code symbol and a codeimmediately followed thereby, but also the relation of those symbols anda code symbol further immediately followed thereby that is pre-read.

An output of the EFM modulator 12 is supplied to the optical modulator2. The EFM modulator 12 generates a record signal of the CD EFM frameformat. The record signal is supplied to the optical modulator 2. Withmodulated laser light modulated by the optical modulator 2, photoresiston the glass master disc 4 is exposed. A developing process and anelectroplating process are performed for the glass master disc 4 onwhich data has been recorded in such a manner. As a result, a metalmaster is produced. With the metal master, a mother disc is produced.With the mother disc, a stamper is produced. With the stamper, asubstrate for an optical disc is produced by the compression moldingmethod, the injection molding method, or the like. A reflection layermade of A1 or the like is formed on the produced disc substrate. On thereflection layer, a protection layer is formed. As a result, an opticaldisc is produced.

FIG. 3 shows the data structure of one EFM frame of the CD format. Inthe CD format, parity Q and parity P which are four symbols each aremade from a total of 12 samples (24 symbols) of two-channel digitalaudio data. 33 symbols (264 data bits) of which one symbol of sub codedata is added to a total of 32 symbols is treated as one block. In otherwords, one frame which has been EFM modulated contains sub code data ofone symbol, data of 24 symbols, a Q parity of four symbols, and a Pparity of four symbols.

In the EFM modulating system, each data symbol (eight data bits) isconverted into a code symbol of 14 channel bits. Merging bits of threebits are placed between two code symbols of 14 channel bits each. Inaddition, a frame sync pattern is added at the beginning of a frame.When the period of a channel bit is T, a frame sync pattern is a patternof which 11T, 11T, and 2T are in succession. Since such a pattern doesnot take place according to the EFM conversion rule, a frame sync can bedetected with such a special pattern. The total number of bits of oneEFM frame is 588 channel bits. The frame frequency is 7.35 kHz.

As shown in FIG. 4, a block of 98 EFM frames is referred to as sub codeframe (or sub code frame). A sub code frame of which 98 frames arearranged in succession is composed of a sync pattern portion thatidentifies the beginning of the sub code frame, a sub code portion, anda data and parity portion. A sub code frame is equivalent to 1/75 secondof a reproduction time of a conventional CD.

The sub code portion is composed of 98 EFM frames. Two frames at thebeginning of the sub code portion are synchronous patterns S0 and S1 ofthe sub code frame and patterns of an EFM out-of-rule. The individualbits of the sub code portion compose P, Q, R, S, T, U, V, and Wchannels.

Although R channel to W channel may be used for special purposes such asa still picture or a sub-title display of so-called Karaoke, they arenormally not used. P channel and Q channel are used for a track positioncontrolling operation for the pickup during reproduction of digital datarecorded on the disc.

P channel is used to record a signal whose level is “0” in a so-calledlead-in area, which is an inner peripheral portion of the disc and asignal whose level alternately varies between “0” and “1” atpredetermined periods in a so-called lead-out area, which is an outerperipheral portion of the disc. P channel is also used to record asignal whose level is “1” between music programs in a program areaformed between the lead-in area and the lead-out area of the disc and asignal whose level is “0” in the other area. P channel is used to detectthe beginning of each music program during reproduction of digital audiodata recorded on the CD.

Q channel is provided to more acutely control digital audio datarecorded on the CD during reproduction. One sub code frame of Q channelis composed of a control bit portion, an address bit portion, a data bitportion, and a CRC (Cyclic Redundancy Check) bit portion as shown inFIG. 5.

Thus, in the program area (except for an area between music programs),as shown in FIG. 6A and FIG. 6B, a data symbol in the sub code portionis “00h” or “40h”. In other words, R to W channels are not used, whereasP channel and Q channel are used. In an area between music programs, Pchannel is “0”. When data of Q channel is “0”, as shown in FIG. 6A, adata symbol in the sub code portion is “00h”. When data of Q channel is“1”, as shown in FIG. 6B, a data symbol in the sub code portion is“40h”.

According to the present embodiment, a special pattern is placed in sucha manner that merging bits selected in the EFM modulation when DSV iscontrolled according to the relation of an immediately preceded codesymbol and a code immediately followed thereby are different frommerging bits selected in the EFM modulation when DSV is controlledaccording to the relation of that code symbol and a code symbol furtherimmediately followed thereby. Next, such a special pattern will bedescribed.

As described above, in the CD format, as a modulating system used torecord data, the EFM modulation is used. In the EFM modulation, eightdata bits (sometimes referred to as data symbol) are converted into 14channel bits (sometimes referred to as code symbol). In addition, when14-bit code symbols are connected, merging bits are placed therebetweenso as to satisfy the run length limit conditions and keep DC balance.

FIG. 7 to FIG. 12 show an example of the EFM conversion table thatconverts data bits of eight bits into channel bits of 14 bits. In FIG. 7to FIG. 12, data symbols are represented in hexadecimal notation (00 toFF), decimal notation (0 to 255), and binary notation (d1 . . . , d8).“1” of a code symbol represents that a waveform is inverted. The minimumtime length of the EFM modulation (time length in which the number of 0sbetween two is of a record signal becomes the minimum) Tmin is 3T. Themaximum time length of the EFM modulation (time length in which thenumber of 0s between two 1s of a record signal becomes the maximum) Tmaxis 11T. The pit length equivalent to T is the shortest pit length. Allcode symbols shown in FIG. 7 to FIG. 12 satisfy rules of which theminimum time length is 3T and the maximum time length Tmax is 11T(hereinafter they are referred to as run length limit conditions).

Between two code symbols of 14 bits each, three merging bits are placedso as to satisfy the foregoing run length limit conditions and keep theDC balance. As merging bits, there are four types of patterns “000”,“001”, “010”, and “100”. Among the four patterns of merging bits, onepattern that satisfies the run length limit conditions of which theminimum time length Tmin is 3T and the maximum time length is 11T and ofwhich DSV (Digital Sum Variation) is close to “0” is selected.

Next, an example of which merging bits are used to connect code symbolsof 14 bits each will be described with reference to FIG. 13A to FIG.13D. The following example is described in “Book on Compact Disc(Version 3) [translated title; written in Japanese]”, published byOhm-Sha Publishing Company, Japan, Mar. 25, 2001.

As shown in FIG. 13A, the cast that a preceded pattern of 14 bits endswith “010” and a data symbol immediately followed thereby is “01110111”(“77h” in hexadecimal notation and “119” in decimal notation) will beconsidered. The data symbol is converted into a code symbol of 14 bits(00100010000010) according to the conversion table shown in FIG. 7 toFIG. 12. In FIG. 13A to FIG. 13D, before timing t0, the code symbol of14 bits ends. At timing t₁ after the period of merging bits, theimmediately followed code symbol of 14 bits starts. At timing t₂, thefurther followed pattern of 14 bits starts. The waveform is inverted at“1”.

When the preceded pattern of 14 bits ends with (010) and the immediatelyfollowed code symbol of 14 bits is converted into (00100010000010), ifthe merging bits (100) of the foregoing four patterns are used, thecondition of Tmin=3T is not satisfied. Thus, the merging bits (100)cannot be used. From the rest of patterns of the merging bits (000),(010), and (001), one pattern that decrease DSV is selected.

DSV is a cumulative value of which when a waveform is in a high level,“+1” is counted and when a waveform is in a low level, “−1” is counted.As an example, it is assumed that DSV at timing to is (−3).

FIG. 13B shows the case that “000” are used as merging bits. FIG. 13Cshows the case that “010” are used as merging bits. FIG. 13D shows thecase that “001” are used as merging bits.

As shown in FIG. 13B, when (000) are used as merging bits, DSV is “−3”at timing t0. DSV is “+3” in period (t0 to t1). DSV is “+2”(+2−4+6−2=+2) in period (t1 to t2). Thus, DSV is (−3+3+2=+2) at timingt2.

As shown in FIG. 13C, when (010) are used as merging bits, DSV is “−3”at timing t0. DSV is “−1” (+1−2=−1) in period (t0 to t1). DSV is “−2”(−2+4−6+2=−2) in period (t1 to t2). Thus, DSV is (−3−1−2=−2) at timingt2.

As shown in FIG. 13D, when (001) are used as merging bits, DSV is “−3”at timing t0. DSV is “+1” (+2−1=1) in period (t0 to t1). DSV is “−2”(−2+4−6+2=−2) in period (t1 to t2). Thus, DSV is (−3+1−2=−4) at timingt2.

Thus, when the preceded pattern of 14 bits ends with (010) and theimmediately followed code symbol of 14 bits is converted into(00100010000010), merging bits that satisfy the run length limitconditions (Tmin=3T and Tmax=11T) are (000), (010), and (001). When(000) are used as merging bits, DSV becomes “+2”. When (010) are used asmerging bits, DSV becomes “−6”. When (001) are used as merging bits, DSVbecomes “−4”. Thus, merging bits (000) of which DSV becomes closest to“0” at timing t2 are selected as merging bits in period (t0 to t1).

Thus, when code symbols of 14 bits each are connected, merging bits areselected from four patterns of (000), (001), (010), and (100) thatsatisfy the rules (Tmin=3T and Tmax=11T) and of which the cumulativevalue of DSV approaches to “0”. As a result, the run length limitconditions (Tmin=3T and Tmax 11T) can be satisfied. In addition, DSVconverges to “0”. In such a manner, in the EFM, when merging bits areproperly selected, DSV can be caused to converge to “0”. When DSVconverges to “0”, the DC balance is kept. When the DC balance is notkept, the slice level in which data is reproduced goes wrong. As aresult, an error increases and the spindle servo gets disordered.Substantially, the reproducing operation cannot be performed.

However, even if merging bits are selected, DSV does not always convergeto “0” in every pattern. In other words, in some special patterns, DSVdoes not converge to “0”.

For example, a pattern of which data symbols “FAh” are repeated as shownin FIG. 14A is considered. When a data symbol “FAh” is converted into acode symbol of 14 bits according to the foregoing conversion table, acode symbol (10010000010010) is obtained. As merging bits that connectcode symbols (10010000010010), into which data symbols “FAh” have beenconverted, as shown in FIG. 14B, (000) are unconditionally used. This isbecause other merging bits ((001), (010), and (100)) do not satisfy therun length limit condition Tmin=3T.

FIG. 14C shows a waveform of the pattern shown in FIG. 14B. As is clearfrom FIG. 14C, in the pattern, DSV negatively increases by “−5”(−3+3−6+3−2=−5) in period (t10 to f11). Thus, in a pattern of which datasymbols “FAh” are repeated, DSV negatively increases, not converges to“0”.

Next, a pattern of which data symbols “FBh” are repeated as shown inFIG. 15A is considered. When a data symbol “FBh” is converted into acode symbol of 14 bits according to the foregoing conversion table, acode symbol (10001000010010) is obtained. As merging bits that connectcode symbols (10001000010010), into which data symbols “FBh” have beenconverted, due to the run length limit conditions (Tmin=3T andTmax=11T), (000) are unconditionally selected as shown in FIG. 15B.

FIG. 15C shows a waveform of the pattern shown in FIG. 15B. As is clearfrom FIG. 15C, when code symbols (10001000010010) of 14 channel bitseach, into which data symbols “FBh” have been converted, are connectedwith merging bits (000), DSV negatively increases by (−3+4−5+3−2=−3) inperiod (t20 to t21). Thus, in a pattern of which data symbols “FBh” arerepeated, DSV negatively increases, not converges to “0”.

As shown in FIG. 16A, a pattern of which data symbols “FAh” and “FBh”are alternately repeated. When a data symbol “FAh” is converted into acode symbol of 14 bits according to the foregoing conversion table, acode symbol (10010000010010) is obtained. When a data symbol “FBh” isconverted into a code symbol of 14 bits according to the foregoingconversion table, a code symbol (10001000010010) is obtained. As mergingbits that connect the code symbol (10010000010010), into which the datasymbol “FAh” has been converted, and the code symbol (10001000010010),into which the data symbol “FBh” has been converted, due to the runlength limit condition (Tmin=3T), (000) are unconditionally selected asshown in FIG. 16B.

FIG. 16C shows a waveform of the pattern shown in FIG. 16B. As is clearfrom FIG. 16C, when the code symbol (10010000010010), into which thedata symbol “FAh” has been converted, and the code symbol(10001000010010), into which the data symbol “FBh” has been converted,are connected with the merging bits (000), as the waveform shown in FIG.16C, DSV negatively increases by “−5” (−3+3−6+3−2=−5) in period (t30 tot31). DSV negatively increases by “−3” (−3+4−5+3−2=−3) in period (t31 tot32). Thus, in a pattern of which “FAh” and “FBh” are alternatelyrepeated, DSV negatively increases, not converges to “0”.

Thus, in the foregoing special patterns, merging bits cannot beselected. Consequently, using flexibility of merging bits, the functionfor causing DSV to converge to “0” does not work. As long as such a datapattern continues, DSV positively or negatively continues to increase.Unless DSV converges to “0”, the DC balance is lost, an error increases,and the servo gets disordered. Substantially, the reproducing operationfor the disc cannot be performed.

It is clear that special patterns of which DSV does not converge to “0”are not limited to the foregoing examples. For example, when a convertedcode symbol of 14 bits that ends with “0T” or “1T” and a converted codesymbol of 14 bits that begins with “0T” or “11T” are connected, mergingbits cannot be selected. Thus, there is a possibility of which DSV doesnot converge to “0”.

As described above, as merging bits that connect code symbols of 14 bitseach, merging bits are selected from (000), (100), (010), and (001) thatsatisfy the run length limit conditions (Tmin=3T and Tmax=11T) and ofwhich DSV approaches to “0”. Merging bits are selected so that theysatisfy the run length limit conditions (Tmin=3T and Tmax=11T) and thecumulative value of DSV approaches to “0”.

However, there is a special pattern of which when merging bits areselected according to the relation of an immediately preceded codesymbol and a code symbol immediately followed thereby so that DSVapproaches to “0”, DSV increases according to the relation of those codesymbol and a code symbol further immediately followed thereby. In otherwords, there is a special pattern of which merging bits selected in theEFM modulation when DSV is controlled according to the relation of animmediately preceded code symbol and a code symbol immediately followedthereby is different from merging bits selected in the EFM modulationwhen DSV is controlled according to the relation of those symbols and acode symbol further immediately followed thereby. In such a specialpattern, it is necessary to select merging bits according to not onlythe relation of an immediately preceded code symbol and a code symbolimmediately followed thereby, but also the relation of those code symboland a code symbol further immediately followed thereby.

Next, a pattern of which a data symbol “90h” is followed by data symbols“B9h” and “9Ah” that are alternately repeated is considered.

When a data symbol “90h” is converted into a code symbol of 14 bitsaccording to the foregoing conversion table, a code symbol of 14 bits(10000000100001) is obtained. When the immediately preceded code symbolends with “00”, (the sub code is “00h” or “40h” and the code symbolthereof ends with “00”), merging bits that immediately precede the codedata (10000000100001) are (000) or (100) due to the run length limitconditions (Tmin=3T and Tmax=11T). The merging bits (000) or (100) areselected depending on DSV. FIG. 17B and FIG. 17C show the case thatmerging bits (000) have been selected. FIG. 17D and FIG. 17E show thecase that (100) are selected as merging bits.

In FIG. 17A to FIG. 17E, it is assumed that the cumulative value of DSVis (−50) until timing t50. As shown in FIG. 17B, when (000) are selectedas merging bits, DSV varies by “+1” (−3+8−5+1=+1) in period (t50 tot51). DSV is (−49) at timing t51.

In contrast, as shown in FIG. 17D, when (100) are selected as mergingbits, DSV varies by “−1” (+3−8+5−1=−1) in period (t50 to t51). DSV is“−51” at timing t51.

Thus, when (000) are selected as merging bits, DSV is “−49” at timingt51. When (100) are selected as merging bits, DSV is “−51” at timingt51. Thus, normally, (000) are selected as merging bits.

However, in such a pattern, when (000) are selected as merging bits, asdenoted by broken line L1 of FIG. 18, DSV negatively increases. Thus,DSV does not converge to “0”. On the other hand, when (100) are selectedas merging bits, as denoted by broken line L2 of FIG. 18, DSV convergesto “0”.

In other words, when (000) are selected as merging bits, thereafter, thewaveform varies as shown in FIG. 17C.

As shown in FIG. 17A to FIG. 17E, a data symbol “90h” is followed by adata symbol “B9h”. When the data symbol “B9h” is converted into a codesymbol of 14 bits according to the foregoing conversion table, a codesymbol “10000000001001” is obtained. As merging bits placed between thecode data (10000000100001), into which the data symbol “90h” has beenconverted, and the code data (10000000001001), into which the datasymbol “B9h” has been converted, due to the run length limit conditions(Tmin=3T and Tmax=11T), merging bits (000) are unconditionally selected.When (000) are selected as merging bits, DSV varies by “−5”(+3−10+3−5=−5) in period (t51 to t52). DSV is “−54” at timing t52.

The data symbol “B9h” is followed by a data symbol “9Ah”. When the datasymbol “9Ah” is converted into a code symbol of 14 bits according to theforegoing code symbol, a code symbol (10010000000001) is obtained. Asmerging bits placed between the code data (10000000001001), into whichthe data symbol “B9h” has been converted, and the code symbol(10010000000001), into which the data symbol “9Ah” has been converted,due to the run length limit conditions (Tmin=3T and Tmax=11T), (000) areunconditionally selected. When (000) are selected as merging bits, DSVvaries by “−9” (−3+3−10+1=−9) in period (t52 to t53). DSV is “−63” attiming t53.

Thereafter, DSV varies by “−5” in the period of the data symbol “B9h”.DSV varies by “−9” in the period of the data symbol “9Ah”. DSV varies asdenoted by broken line L1 of FIG. 18. Thereafter, since the data symbols“9Ah” and “B9h” are alternately repeated, DSV negatively increases.Thus, DSV does not converge to “0”.

In contrast, FIG. 17E shows a waveform in the case that (100) areselected as the first merging bits.

As shown in FIG. 17A to FIG. 17E, the data symbol “90h” is followed bythe data symbol “B9h”. When the data symbol “B9h” is converted into acode symbol of 14 bits, a code symbol (10000000001001) is obtained. Asmerging bits placed between the code data (10000000100001), into whichthe data symbol “90h” has been converted, and the code data(10000000001001), into which the data symbol “B9h” has been converted,due to the run length limit conditions (Tmin=3T and Tmax=11T), (000) areunconditionally selected. When (000) are selected as merging bits, DSVvaries by “+5” (−3+10−3+1=+5) in period (t51 to t52). DSV is “−46” attiming t52.

The data symbol “B9h” is followed by the data symbol “9Ah”. When thedata symbol “9Ah” is converted into a code symbol of 14 bits, a codesymbol (10010000000001) is obtained. As merging bits placed between thecode data (10000000001001), into which the data symbol “B9h” has beenconverted, and the code data (10010000000001), into which the datasymbol “9Ah” has been converted, due to the run length limit conditions(Tmin=3T and Tmax=11T), (000) are unconditionally selected. When (000)are selected as the merging bits, DSV varies by “+9” (+3−3+10−1=+9) inperiod (t52 to t53). DSV is “−37” at timing t53.

Thereafter, DSV varies by “+5” in the period of the data symbol “B9h”.DSV varies by “+9” in the period of the data symbol “9Ah”. DSV varies asdenoted by broken line L2 of FIG. 18. Thus, thereafter, the data symbol“9Ah” and the data symbol “B9h” are alternately repeated. As a result,DSV positively increases. As denoted by broken line L2 of FIG. 18, DSVconverges to “0”.

In such a special pattern, when merging bits are selected so that DSVapproaches to “0” according to the relation of an immediately precededcode symbol and a code symbol immediately followed thereby, thereafter,DSV positively or negatively increases. In such a pattern, it isnecessary to select merging bits according to not only the relation ofan immediately preceded code symbol and a code symbol immediatelyfollowed thereby, but also the relation of that code symbol and a codesymbol further immediately followed thereby. Such a pattern is notlimited to the foregoing example.

In the foregoing example, merging bits of which DSV approaches to “0”according to the relation of an immediately preceded code symbol and acode symbol immediately followed thereby are different from merging bitsof which DSV approaches to “0” according to the relation of that codesymbol and a code symbol further immediately followed thereby. However,according to the present invention, a special pattern of which mergingbits or a conversion pattern selected when DSV is calculated accordingto the relation of one code symbol and A code symbols immediatelyfollowed thereby is different from merging bits or a conversion patternselected when DSV is calculated according to the relation of one codesymbol and B (where B >A) code symbols immediately followed thereby canbe used. The predetermined number A is normally “1”.

As described above, in the EFM modulation, using the flexibility ofmerging bits, DSV is caused to converge to “0”. However, it is clearthat in a special pattern merging bits are unconditionally selected andDSV cannot be caused to converge to “0”.

It is clear that in a special pattern merging bits selected in the EFMmodulation when DSV is controlled according to the relation of animmediately preceded code symbol and a code symbol immediately followedthereby are different from merging bits selected in the EFM modulationwhen DSV is controlled according to the relation of that code symbol anda code symbol further immediately followed thereby.

In the case that such a special pattern is contained in an originaldisc, when data is reproduced from the original disc, the reproduceddata is encoded by a conventional encoder, and the encoded data isrecorded on a recording medium such as a CD-R disc, then a recordingmedium of which DSV does not converge to “0” is produced. As a result,the reproduced data would not been correctly read from the medium.

In the example, as described above, a special pattern of which mergingbits selected in the EFM modulation when DSV is controlled according tothe relation of an immediately preceded code symbol and a code symbolimmediately followed thereby are different from merging bits selected inthe EFM modulation when DSV is controlled according to the relation ofthat code symbol and a code symbol further immediately followed therebyis used.

In other words, in the master apparatus shown in FIG. 1, which producesan original CD, the EFM modulator 12, the merging bit selecting portion14, and the DSV controlling portion 15 select merging bits according tonot only the relation of an immediately preceded code symbol and a codesymbol immediately followed thereby, but also the relation of that codesymbol and a code symbol further immediately followed thereby that ispre-read. Thus, even if an original recording medium produced by themaster apparatus contains a special pattern shown in FIG. 2A, FIG. 2B,or FIG. 17A to FIG. 17E, merging bits are selected so that DSV convergesto “0”. In contrast, when data of an original recording medium is copiedto a CD-R disc or the like, the EFM modulating portion selects mergingbits of which DSV approaches to “0” according to the relation of only animmediately preceded code symbol and a code symbol immediately followedthereby not the relation of that code symbol and a code symbol furtherimmediately followed thereby that is pre-read. Thus, when a specialpattern shown in FIG. 2A, FIG. 2B, or FIG. 17A to FIG. 17E is reproducedfrom a copied recording medium, since DSV increases, the reproducingoperation cannot be performed.

FIG. 19 is a flow chart showing an example of a process for selectingmerging bits according to not only the relation of an immediatelypreceded code symbol and a code symbol immediately followed thereby, butalso the relation of that code symbol and a code symbol furtherimmediately followed thereby that is pre-read as with the EFM modulator12, the merging bit selecting portion 14, and the DSV controllingportion 15 of the mastering apparatus shown in FIG. 1.

As shown in FIG. 20A, an immediately preceded data symbol of eight bitsis denoted by D0, a current data symbol of eight bits is denoted by D1,a data symbol of eight bits immediately followed thereby is denoted byD2, and data symbols further immediately followed thereby are denoted byD3, D4, . . . , and so forth.

As shown in FIG. 20B, these data symbols D0, D1, D2, D3, D4, . . . andso forth are converted into code symbols of 14 bits each. The convertedcode symbols are denoted by d0, d1, d2, d3, . . . , and so forth. Theposition of merging bits placed between the code symbol d0 and the codesymbol d1 is denoted by (A=1). The position of merging bits placedbetween the code symbol d1 and the code symbol d2 is denoted by (A=2).Alternatives of four patterns of merging bits of (A=1) are denoted byMPn (1) ((MP0 (1)=000), (MP1 (1)=001), (MP2 (1)=010), and (MP3 (1)=100).Alternatives of four patterns of merging bits of (A=2) are denoted byMPn (2) ((MP0 (2)=000), (MP1 (2)=001), (MP2 (2)=010), and (MP3(2)=100)).

In FIG. 19, when merging bits placed between the code symbol d0 and thecode symbol d1 immediately followed thereby are selected, the datasymbol D1 of eight bits and the data symbol D2 immediately followedthereby are input (at step S1). The data symbols D1 and D2 are convertedinto code symbols d1 and d2 of 14 bits each according to the conversiontable (at step S22). Alternative merging bits placed between the codesymbol d0 and the code symbol d1 (A1) and alternative merging bitsplaced between the code symbol d1 and the code symbol d2 (A2) areselected (at step S3).

First of all, (A=1), (n (1)=0) are set. With merging bits MP0 (1) (MP0(1)=000), the code symbol do and the code symbol d1 (at position A=1)are tried to be connected (at step S4). With the merging bits MP0 (1),the code symbol d0 and the code symbol d1 are tried to be connected andit is determined whether or not the run length limit condition of theminimum inversion period (Tmin=3T) is satisfied (at step S5). When thecondition of the minimum inversion period (Tmin=3T) is satisfied, it isdetermined whether or not the run length limit condition of the maximuminversion period (Tmax=11T) is satisfied (at step S6).

When the condition of the minimum inversion period (Tmin=3T) is notsatisfied at step S5 or when the condition of the maximum inversionperiod (Tmax=11T) is not satisfied at step S6, n (1) is incremented (atstep S7). With the merging bits MPn+1 (1), the code symbol d0 and thecode symbol d1 are tried to be connected (A=1) and it is determinedwhether or not the run length limit condition of the minimum inversionperiod (Tmin=3T) is satisfied (at step S5). When the condition of theminimum inversion period (Tmin=3T) is satisfied, it is determinedwhether or not the run length limit condition of the maximum inversionperiod (Tmax=11T) is satisfied (at step S6).

When the condition of the minimum inversion period (Tmin=3T) issatisfied at step S5 and when the condition of the maximum inversionperiod (Tmax=11T) is satisfied at step S6, as merging bits that satisfythe run length limit conditions of (A=1), the information is stored (atstep S8). Thereafter, it is determined whether or not (n (1)=3) issatisfied (at step S9). When (n (1)=3) is not satisfied, n (1) isincremented (at step S7). With the merging bits MPn+1 (1), the codesymbol d0 and the code symbol d1 are tried to be connected (A=1) and itis determined whether or not the run length limit condition of theminimum inversion period (Tmin=3T) is satisfied (at step S5). When thecondition of the minimum inversion period (Tmin=3T) is satisfied, it isdetermined whether or not the run length limit condition of the maximuminversion period (Tmax=11T) is satisfied (at step S6).

By repeating the foregoing process, with the merging bits MP0 (1) (MP0(1)=000), MP1 (1) (MP1 (1)=001), MP2 (1) (MP2 (1)=010), MP3 (1) (MP3(1)=100), the code symbol d0 and the code symbol d1 are connected (A=1)and it is determined whether or not the run length limit conditions ofthe minimum inversion period (Tmin=3T) and the maximum inversion period(Tmax=11T) are satisfied. The information of merging bits that satisfythe run length limit conditions is stored at step S8.

When the determined result at step S9 represents that (n (1)=3) issatisfied, it is determined whether or not (A=2) is satisfied (at stepS10). When (A=2) is not satisfied, A is incremented (at step S11).Thereafter, the flow returns to step S5.

Thereafter, (A=2), (n (2)=0) are set. With the merging bits MPO (2) (MPO(2)=000), the code symbol d1 and the code symbol d2 are tried to beconnected (A=2). With the merging bits MP0 (2), the code symbol d1 andthe code symbol d2 are tried to be connected and it is determinedwhether or not the run length limit condition of the minimum inversionperiod (Tmin=3T) is satisfied (at step S5). When the condition of theminimum inversion period (Tmin=3T) is satisfied, it is determinedwhether or not the run length limit condition of the maximum inversionperiod (Tmax=11T) is satisfied (at step S6).

When the condition of the minimum inversion period (Tmin=3T) is notsatisfied at step S5 or when the condition of the maximum inversionperiod (Tmax=11T) is not satisfied at step S6, n (2) is incremented (atstep S7). With the merging bits Mpn+1 (2), the code symbol d1 and thecode symbol d2 are tried to be connected (A=2) and it is determinedwhether or not the run length limit conditions of the minimum inversionperiod (Tmm=3T) is satisfied (at step S5). When the condition of theminimum inversion period (Tmin=3T) is satisfied, it is determinedwhether or not the run length limit condition of the maximum inversionperiod (Tmax=11T) is satisfied (at step S6).

When the condition of the minimum inversion period (Tmin=3T) issatisfied at step S5 and when the condition of the maximum inversionperiod (Tmax=11T) is satisfied at step S6, as merging bits that satisfythe run length limit conditions of (A=2), this information is stored (atstep S8). Thereafter, it is determined whether or not (n (2)=3) issatisfied (at step S9). When (n (2)=3) is not satisfied, n (2) isincremented (at step S7). With the merging bits MPn+1(2), the codesymbol d1 and the code symbol d2 are tried to be connected (A=2) and itis determined whether or not the run length limit condition of theminimum inversion period (Tmin=3T) is satisfied (at step S5). When thecondition of the minimum inversion period (Tmin=3T) is satisfied, it isdetermined whether or not the run length limit condition of the maximuminversion period (Tmax=11T) is satisfied (at step S6).

By repeating the foregoing process, with the merging bits MP0 (2)(MP0(2)=000), MP1 (2) (MP1 (2)=001), MP2 (2) (MP2 (2)=010), MP3 (2) (MP3(2)=100), the code symbol d1 and the code symbol d2 are connected (A=2)and it is determined whether or not the run length limit conditions ofthe minimum inversion period (Tmin=3T) and the maximum inversion period(Tmax=11T) are satisfied. The information of the merging bits thatsatisfy the run length conditions is stored at step S8.

When the determined result at step S9 represents that (n (2)=3) issatisfied, it is determined whether or not (A=2) is satisfied (at stepS9). When (A=2) is satisfied, with a combination of the merging bitinformation that satisfies the run length limit conditions of theminimum inversion period (Tmin=3T) and the maximum inversion period(Tmax=11T) at the position (A=1) stored at step S8 and the merging bitinformation that satisfies the run length limit conditions of theminimum inversion period (Tmin=3T) and the maximum inversion period(Tmax=11T), DSV is calculated. In other words, in a combination of themerging bits MPn (1) that satisfy the conditions and that are placedbetween the immediately preceded code symbol do and the current codesymbol d1 (A=1) and the merging bits MPn (2) that satisfy the conditionsand that are placed between the current code symbol d1 and the codesymbol d2 immediately followed thereby (A=2), DSV is obtained. In thecombination, the minimum value of the absolute values of DSV is selected(at step S12). Thus, merging bits placed between the code symbol d0 andthe current code symbol d1 (A=1) are decided (at step S13).

In the example, merging bits placed between the code symbol d0 and thecode symbol d1 immediately followed thereby (A=1) are decided bypre-reading the code symbol D2 further immediately followed thereby,converting the code symbol D2 into the code symbol d2, and consideringmerging bits selected between the code symbol d1 and the code symbol d2(A=2). In addition, to decide the merging bits, the data symbols D3, D4,. . . and so forth may be pre-read.

FIG. 21 shows an example of the structure of a reproducing apparatusthat reproduces data from an optical disc that has been produced in theforegoing mastering and stamping processes.

Although the structure of the reproducing apparatus is the same as thatof a conventional player or drive, the structure will be described foreasy understanding of the present invention. In FIG. 21, referencenumeral 21 represents a disc as a recording medium produced in theforegoing mastering and stamping processes. Reference numeral 22represents a spindle motor that drives the rotations of the disc 21.Reference numeral 23 represents an optical pickup that reproduces asignal from the disc 21. The optical pickup 23 is composed of asemiconductor laser that radiates laser light to the disc 21, an opticalsystem such as an objective lens, a detector that receives lightreflected from the disc 21, a focus and tracking mechanism, and soforth. The optical pickup 23 is traveled in the radius direction of thedisc 21 by a thread mechanism (not shown).

Output signals of for example a four-divided detector of the opticalpickup 23 are supplied to an RF portion 24. The RF portion 24 calculatesthe output signals of the individual detector elements of thefour-divided detector and generates a reproduction (RF) signal, a focuserror signal, and a tracking error signal. The reproduction signal issupplied to a sync detecting portion 25. The sync detecting portion 25detects a frame sync from the beginning of each EFM frame. The detectedframe sync, the focus error signal, and the tracking error signal aresupplied to a servo portion 26. The servo portion 26 controls therotations of the spindle motor 22 and performs a focus servo and atracking servo of the optical pickup 23 corresponding to a reproducedclock of the RF signal.

Main data that is output from the sync detecting portion 25 is suppliedto an EFM demodulator 27. The EFM demodulator 27 performs an EFMdemodulating process for the main data. Main digital data is suppliedfrom the EFM demodulator 27 to a CIRC decoder 28. The CIRC decoder 28performs an error correcting process for the main digital data. Aninterpolating circuit 29 interpolates the main digital data and outputsthe interpolated data as reproduced data to an output terminal 30. Subcode data is supplied from the EFM demodulator 27 to a system controller32.

The system controller 32 is composed of a microcomputer. The systemcontroller 32 controls operations of the whole reproducing apparatus. Inassociation with the system controller 32, an operation button anddisplay portion 33 is disposed. The system controller 32 controls theservo portion 26 so as to access a desired position of the digital 21.

According to the present embodiment, as described above, a specialpattern of which merging bits selected in the EFM modulation when DSV iscontrolled according to the relation of an immediately preceded codesymbol and a code symbol immediately followed thereby are different frommerging bits selected in the EFM modulation when DSV is controlledaccording to the relation of that code symbol and a code symbol furtherimmediately followed thereby is recorded on the disc 21. The EFMmodulator 12 of the master apparatus shown in FIG. 1 has the merging bitselecting portion 14 and the DSV controlling portion 15. As shown inFIG. 19, the merging bit selecting portion 14 and the DSV controllingportion 15 perform the merging bit selecting process according to notonly the relation of an immediately preceded code symbol and a codesymbol immediately followed thereby, but also the relation of those codesymbol and a code symbol further immediately followed thereby that ispre-read. Thus, in such a special pattern, merging bits are added sothat DSV finally converges to “0”. Thus, when an original disc 21 isused, the special pattern portion can be reproduced.

However, a conventional CD-R disc recording apparatus selects mergingbits of which DSV approaches to “0” in the EFM modulation according tothe relation of an immediately preceded code symbol and a code symbolimmediately followed thereby. Thus, when data is copied from theoriginal disc 21, in the special pattern of the copied disc, DSV doesnot converge to “0”. As a result, the DC balance is lost and thereproducing operation cannot be performed. Consequently, the copyingoperation can be prevented.

FIG. 22 is a flow chart showing a merging bit controlling processperformed by a conventional EFM modulator disposed in a CD-R disc driveand a CD-RW disc drive.

As shown in FIG. 23A, an immediately preceded data symbol is denoted byD0, a data symbol of eight bits immediately followed thereby is denotedby D1, a data symbol of eight bits further immediately followed therebyis denoted by D2, and other data symbols further immediately followedthereby are denoted by D3, D4, . . . and so forth.

As shown in FIG. 23B, these code symbols D0, D1, D2, D3, D4, . . . andso forth are converted into code symbols of 14 bits. These convertedcode symbols are denoted by d1, d2, d3, . . . and so forth. Alternativesof four patterns of merging bits placed between the code symbol d0 andthe code symbol d1 are denoted by MPn ((MP0=000), MP1 (MP1=001), MP2(MP2=010), and MP3 (MP3=100).

In FIG. 22, when merging bits placed between the code symbol do and thecode symbol d1 immediately followed thereby are selected, the datasymbol D1 of eight bits is input (at step S51). The data symbol D1 isconverted into the code symbol d1 of 14 bits according to the conversiontable (at step S52). Thereafter, merging bits placed between the currentcode symbol d1 and the code symbol d0 immediately preceded thereby areselected (at step S53).

At first, n=0 is set (at step S54). With the merging bits MP0 (MP0=000),the immediately preceded code symbol d0 and the current code symbol d1are tried to be connected (at step S54). With the merging bits MP0, theimmediately preceded code symbol do and the current code symbol d1 aretried to be connected and it is determined whether or not the run lengthlimit condition of the minimum inversion period (Tmin=3T) is satisfied(at step S55). When the condition of the minimum inversion period(Tmin=3T) is satisfied, it is determined whether or not the run lengthlimit condition of the maximum inversion period (Tmax=11T) is satisfied(at step S56).

When the condition of the minimum inversion period (Tmin=3T) is notsatisfied at step S55 or when the condition of the maximum inversionperiod (Tmax =11T) is not satisfied at step S56, n is incremented (atstep S57). With the merging bits MPn+1, the immediately preceded codesymbol d0 and the current code symbol d1 are tried to be connected andit is determined whether or not the run length limit condition of theminimum inversion period (Tmin=3T) is satisfied (at step S55). When thecondition of the minimum inversion period (Tmin=3T) is satisfied, it isdetermined whether or not the run length limit condition of the maximuminversion period (Tmax=11T) is satisfied (at step S56).

When the condition of the minimum inversion period (Tmin=3T) issatisfied at step S55 and when the condition of the maximum inversionperiod (Tmax=11T) is satisfied at step S56, as merging bits that satisfythe run length limit conditions, the information is stored (at stepS58). Thereafter, it is determined whether or not (n=3) is satisfied (atstep S59). When (n=3) is not satisfied, n is incremented (at step S57).With the next merging bits MPn+1, the immediately preceded code symboldo and the current code symbol d1 are tried to be connected and it isdetermined whether or not the run length limit condition of the minimuminversion period (Tmin=3T) is satisfied (at step S55). When thecondition of the minimum inversion period (Tmin=3T) is satisfied, it isdetermined whether or not the run length limit condition of the maximuminversion period (Tmax=11T) is satisfied (at step S56).

By repeating the foregoing process, n advances from “0” to “3”. With themerging bits MP0 (MP0=000), MP1 (MP1=001), MP2 (MP2=010), and MP3(MP3=100), the code symbol d0 and the code symbol d1 are connected andit is determined whether or not the run length limit conditions of theminimum inversion period (Tmin=3T) and the maximum inversion period(Tmax=11T) are satisfied. Information of merging bits that satisfy therun length limit conditions is stored at step S58.

When the determined result at step S59 represents that (n=3) issatisfied, with the merging bits MPn that satisfy the-conditions, DSV iscalculated. In other words, according to the information stored at stepS58, with alternative merging bits MPn that satisfy the conditions andthat are placed between the code symbol d0 and the code symbol d1, DSVis obtained. The minimum value of absolute values of DSV is selected (atstep S60). Thus, merging bits placed between the code symbol d0 and thecode symbol d1 are decided (at step S61).

In the process shown in FIG. 22, merging bits placed between the codesymbol d0 and the code symbol d1 are selected according to only therelation of the immediately preceded code symbol do and the current codesymbol d1. In this case, when a special pattern shown in FIG. 2A, FIG.2B, or FIG. 17A to FIG. 17E is contained, since DSV increases, thereproducing operation cannot be performed.

FIG. 24 shows an outline of a flow of a copying process. A reproducingapparatus denoted by reference numeral 41 reproduces data from anoriginal disc. As described above, the disc 21 is a CD format disc. Aspecial pattern is contained at a predetermined position in such amanner that merging bits selected in the EFM modulation when DSV iscontrolled according to the relation of an immediately preceded codesymbol and a code symbol immediately followed thereby are different frommerging bits selected in the EFM modulation when DSV is controlledaccording to that code symbol and a code symbol further immediatelyfollowed thereby. Reference numeral 43 represents an optical pickup.Reference numeral 44 represents a reproduction signal process portion.Reproduced data is supplied from the reproducing apparatus 41 to arecording process portion 52 of a recording apparatus 51. An opticalpickup 53 records the reproduced data to a disc 54, for example a CD-Rdisc. The recorded contents of the original disc 21 are copied to theCD-R disc 54. The reproducing apparatus 41 and the recording apparatus51 can use a recording and reproducing apparatus structured as a CD-Rdisc drive or a CD-RW disc drive.

As shown in FIG. 25, a sync detecting portion 46 of the reproducingprocess portion 44 detects a frame sync from a reproduced signalsupplied from an input terminal 45. An EFM demodulator 47EFM-demodulates the reproduced signal and supplies the EFM-demodulatedreproduced data to a CIRC decoder 48. The CIRC decoder 48 corrects anerror of the reproduced signal.

As described above, a special pattern shown in FIG. 2A, FIG. 2B, or FIG.17A to FIG. 17E is contained at a predetermined position of the originaldisc 21 in such a manner that merging bits selected in the EFMmodulation when DSV is controlled according to the relation of animmediately preceded code symbol and a code symbol immediately followedthereby are different from merging bits selected in the EFM modulationwhen DSV is controlled according to the relation of that code symbol anda code symbol further immediately followed thereby. The EFM modulator 12of the mastering apparatus shown in FIG. 1 has the merging bit selectingportion 14 and the DSV controlling portion 15. As described above, themerging bit selecting portion 14 and the DSV controlling portion 15perform the process for selecting merging bits according to not only therelation of an immediately preceded code symbol and a code symbolimmediately followed thereby, but also the relation of that code symboland a code symbol further immediately followed thereby that is pre-read.Thus, in such a special pattern, merging bits are added so that DSVfinally converges to “0”. Thus, the special pattern portion can bereproduced.

FIG. 26 shows an outline of the structure of a recording process portion52. Data to be recorded is supplied from an input terminal 55 to a CIRCencoder 56. The CIRC encoder 56 performs a CIRC encoding process for thedata to be recorded. Sub code data is supplied from an input terminal 57to a sub code encoder 58. The sub code encoder 58 formats the sub code.An output of the CIRC encoder 56 and an output of the sub code encoder58 are supplied to a multiplexer 60. In addition, a frame sync issupplied from an input terminal 59 to the multiplexer 60. Themultiplexer 60 arranges those data in a predetermined order. An outputof the multiplexer 60 is supplied to an EFM modulator 61. The EFMmodulator 61 performs an EFM modulating process for data that is outputfrom the multiplexer 60.

As described above, the EFM modulator 61 normally selects merging bitsof which DSV approaches to “0” according to the relation of animmediately preceded code symbol and a code symbol immediately followedthereby. Thus, when a reproduction signal of a portion of a specialpattern at a predetermined position is sent to the EFM modulator 61,merging bits of which DSV approaches to “0” according to the relation ofan immediately preceded code symbol and a code symbol immediatelyfollowed thereby are selected. As a result, DSV increases. The signal isrecoded on a copy disc 54 such as a CD-R disc.

Thus, when the foregoing special pattern is recorded on the originaldisc 21, since a process for selecting merging bits according to notonly the relation of an immediately preceded code symbol and a codesymbol immediately followed thereby, but also the relation of that codesymbol and a code symbol further immediately followed thereby isperformed, in such a special pattern, merging bits are added so that DSVfinally converges to “0”. However, on the copied disc 54, merging bitsof which DSV approaches to “0” according to the relation of animmediately preceded code symbol and a code symbol immediately followedthereby is selected. As a result, merging bits of which DSV increase areadded. Thus, the reproducing operation cannot be performed.

In the foregoing example, on the original disc 21, the process forselecting merging bits according to not only the relation of animmediately preceded code symbol and a code symbol immediately followedthereby, but also the relation of that code symbol and a code symbolfurther immediately followed thereby that is pre-read is performed.However, if the special pattern has been predetermined, merging bits maybe added so that merging bits added to the special pattern are differentfrom merging bits added to the other portion. In this case, as the EFMmodulator 12, a conventional modulator that selects merging bits ofwhich DSV approaches to “0” according to the relation of an immediatelypreceded code symbol and a code symbol immediately followed thereby canbe used.

The permission and prohibition of the use of contents other than thespecial pattern portion can be controlled. In other words, from a discproduced by the master apparatus according to the present invention, thedata pattern portion can be reproduced. On the other hand, when a discis produced by a conventional encoder using an original disc that hasbeen produced by the master apparatus, the special pattern portioncannot be reproduced. Thus, depending on whether or not the patternportion can be read, the disc is detected as an original disc or a copythereof. According to the detected result, it is determined whether ornot contents recorded in other than the data pattern portion can beused. As a result, contents of a copied disc can be prohibited frombeing used.

The special pattern would be placed in a key data portion of encryptedcontents. From a copied disc, the key data portion would be prohibitedfrom being reproduced.

Although the present invention has been shown and described with respectto a best mode embodiment thereof, it should be understood by thoseskilled in the art that the foregoing and various other changes,omissions, and additions in the form and detail thereof may be madetherein without departing from the spirit and scope of the presentinvention. For example, as a modulating system other than EFM, thepresent invention can be applied to EFM Plus. The EFM Plus is a systemthat converts a data symbol of eight bits into a code symbol of 16 bitswithout need to use merging bits. In the EFM Plus, there are specialdata patterns of which DSV increases. Thus, when an encoder that has amodified code conversion table modified from the standard codeconversion table is used, even if a special data pattern is used, DSVcan be prevented from increasing. Thus, it can be determined whether ornot a disc to be used is an original disc of which data was recordedusing an encoder according to the present invention or a copied disc ofwhich data was recorded using a conventional encoder.

The present invention can be also applied to a multi-session opticaldisc on which for example CD-DA formatted data and CD-ROM formatted dataare recorded. As information that is recorded to an optical disc, thereare various types of data such as audio data, video data, still picturedata, character data, computer graphic data, game software, and computerprograms. Thus, the present invention can be applied to for example aDVD video disc and a DVD-ROM disc. In addition, the present inventioncan be applied to not only a disc-shaped data recording medium, but alsoa card-shaped data recording medium.

In the foregoing example, an original disc is produced by the masteringapparatus. Alternatively, an original disc may be produced with a CD-Rdisc or a CD-RW disc. When a special pattern is recorded, since it doesnot require to physically deform a disc with for example pits, even ifan original disc is a recording medium using wobble pits such as a CD-Rdisc or a CD-RW disc, a copy can be protected.

As is clear from the foregoing description, according to the presentinvention, a special pattern is recorded on a recording medium in such amanner that merging bits selected in the EFM modulation when DSV iscontrolled according to the relation of an immediately preceded codesymbol and a code symbol immediately followed thereby are different frommerging bits selected in the EFM modulation when DSV is controlledaccording to the relation of those code symbol and a code symbol furtherimmediately followed thereby. The EFM modulating portion of the masterapparatus that produces an original CD selects merging bits according tonot only the relation of an immediately preceded code symbol and a codesymbol immediately followed thereby, but also the relation of that codesymbol and a code symbol further immediately followed thereby that ispre-read. Thus, even if an original recording medium produced by themaster apparatus contains such a special pattern, merging bits areselected so that DSV converges to “0”. In contrast, when a CD-Rrecording apparatus or the like copies a data of a disc, the EFMmodulating portion of the CD-R recording apparatus selects merging bitsof which DSV approaches “0” according to only the relation of animmediately preceded code symbol and a code symbol immediately followedthereby, not the relation of that code symbol and a code symbol furtherimmediately followed thereby. Thus, in the special pattern, since DSVincreases, the reproducing operation cannot be performed. As a result,the copying operation can be restricted.

According to the present invention, without need to physically deform adisc with for example pits, a copying operation can be prohibited fornot only a disc having wobble pits, but also an original recordingmedium that is a CR-R or CD-RW.

In addition, according to the present invention, since data cannot bereproduced from a copied recording medium, data of an original recordingmedium can be prevented from being directly copied.

In addition, according to the present invention, since a defect is notintentionally placed on an original medium, the present invention can beused as a format standard.

1. A recording method for converting m-bit data into a n-bit (where n>m)data symbol whose run length is restricted and placing a connection bitafter the n-bit data symbol so that the cumulative value of DCcomponents per unit time becomes small, the recording method comprisingthe steps of: selecting a first connection bit to be added to animmediately preceding data symbol from a plurality of connection bitsaccording to at least one first connection bit that can be added betweenthe immediately preceding data symbol and a first data symbolimmediately following the immediately preceding data symbol andaccording to at least one second connection bit that can be addedbetween the first data symbol and at least one second data symbolimmediately following the first data symbol; adding the selected firstconnection bit to the immediately preceding data symbol so as togenerate record data; and recording the generated record data on arecording medium.
 2. The recording method as set forth in claim 1,wherein the selecting step comprises the steps of: selecting a firstgroup including at least one first connection bit that can be addedbetween the immediately preceding data symbol and the first data symbolimmediately following the immediately preceding data symbol; selecting asecond group including at least one second connection bit that can beadded between the first data symbol and the at least one second datasymbol immediately following the first data symbol; and selecting thefirst connection bit from the selected first group and the secondconnection bit from the selected second group so that the cumulativevalue of the DC components becomes small.
 3. The recording method as setforth in claim 2, wherein the first connection bit selecting step isperformed by selecting the first connection bit so that when theselected first connection bit and the selected second connection bit arecombined, the cumulative value of the DC components becomes small.
 4. Arecording method for converting m-bit data into a n-bit (where n>m) datasymbol whose run length is restricted and adding a connection bit afterthe n-bit data symbol so that the cumulative value of DC components perunit time becomes small, the recording method comprising the steps of:selecting a first connection bit to be added to an immediately precedingdata symbol, when the immediately preceding data symbol is a specialdata symbol, from a plurality of connection bits according to at leastone first connection bit that can be added between the immediatelypreceding data symbol and a first data symbol immediately following theimmediately preceding data symbol and according to at least one secondconnection bit that can be added between the first data symbol and atleast one second data symbol immediately following the first datasymbol; adding the selected first connection bit to the immediatelypreceding data symbol so as to generate record data; and recording thegenerated record data on a recording medium.
 5. The recording method asset forth in claim 4, wherein the selecting step comprises the steps of:selecting a first group including at least one first connection bit thatcan be added between the immediately preceding data symbol and the firstdata symbol immediately following the immediately preceding data symbol;selecting a second group including at least one second connection bitthat can be added between the first data symbol and the at least onesecond data symbol immediately following the first data symbol; andselecting the first connection bit from the selected first group and thesecond connection bit from the selected second group so that thecumulative value of the DC components becomes small.
 6. The recordingmethod as set forth in claim 5, wherein the first connection bitselecting step is performed by selecting the first connection bit sothat when the selected first connection bit and the selected secondconnection bit are combined, the cumulative value of the DC componentsbecomes small.
 7. The recording method as set forth in claim 4, whereinthe second connection bit added between the first data symbol and thesecond data symbol is unconditionally selected when the first datasymbol is selected according to the immediately preceding data symboland the first data symbol, with the special data symbol.
 8. Therecording method as set forth in claim 4, wherein the m-bit data ismodulated according to an 8-14 modulating system.
 9. A recording methodfor converting m-bit data into n-bit (where n>m) data whose run lengthis restricted and recording the converted data on a recording medium,the recording method comprising the step of: selecting a first n-bitdata according to an immediately preceding n-bit data, the first n-bitdata immediately following the immediately preceding n-bit data, and asecond n-bit data immediately following the first n-bit data so that thecumulative value of DC components per unit time becomes small, whereinthe n-bit data is composed of a n1-bit data symbol and n2-bit (=n n1)connection bits immediately following the n1-bit data symbol andselected from a plurality of connection bits so that the cumulativevalue of DC components per unit time becomes small; and selecting afirst connection bit to be added to the immediately preceding datasymbol according to at least one connection bit that can be addedbetween the immediately preceding data symbol and the first data symboland at least one second connection bit that can be added between thefirst data symbol and the second data symbol.
 10. The recording methodas set forth in claim 9, wherein the selecting step comprises the stepsof: selecting a first group including at least one first connection bitthat can be added between the immediately preceding data symbol and thefirst data symbol immediately following the immediately preceding datasymbol; selecting a second group including at least one secondconnection bit that can be added between the first data symbol and thesecond data symbol; and selecting the first connection bit from theselected first group and the second connection bit from the selectedsecond group so that the cumulative value of the DC components becomessmall.
 11. The recording method as set forth in claim 10, wherein thefirst connection bit selecting step is performed by selecting the firstconnection bit so that when the selected first connection bit and theselected second connection bit are combined, the cumulative value of theDC components becomes small.
 12. The recording method as set forth inclaim 9, wherein the m-bit data is modulated according to an 8-14modulating system.
 13. The recording method as set forth in claim 9,wherein the m-bit data is modulated according to an 8-16 modulatingsystem.
 14. The recording method as set forth in claim 9, wherein thefirst connection bit is selected when the immediately preceding datasymbol is a special symbol.
 15. The recording method as set forth inclaim 14, wherein the selecting step comprises the steps of: selecting afirst group including at least one first connection bit that can beadded between the immediately preceding data symbol and the first datasymbol immediately following the immediately preceding data symbol;selecting a second group including at least one second connection bitthat can be added between the first data symbol and the second datasymbol; and selecting the first connection bit from the selected firstgroup and the second connection bit from the selected second group bitso that the cumulative value of the DC components becomes small.
 16. Therecording method as set forth in claim 15, wherein the first connectionbit selecting step is performed by selecting the first connection bit sothat when the selected first connection bit and the selected secondconnection bit are combined, the cumulative value of the DC componentsbecomes small.
 17. The recording method as set forth in claim 14,wherein, the second connection bit added between the first data symboland the second data symbol is unconditionally selected when the firstdata symbol is selected according to the immediately preceding datasymbol and the first data symbol, with the special data symbol.
 18. Arecording apparatus, comprising: an encoding process portion configuredto perform an encoding process for input data; a converting portionconfigured to convert m-bit data that is output from the encodingprocessing portion into n-bit (where n>m) data whose run length isrestricted by selecting a first n-bit data according to an immediatelypreceding n-bit data, the first n-bit data immediately following theimmediately preceding n-bit data, and a second n-bit data immediatelyfollowing the first n-bit data so that the cumulative value of DCcomponents per unit time becomes small, and select a first connectionbit to be added to an immediately preceding data symbol according to afirst group including at least one first connection bit that can beadded between the immediately preceding data symbol and a first datasymbol and a second group including at least one second connection bitthat can be added between the first data symbol and a second datasymbol, wherein the n-bit data is composed of a n1-bit data symbol andn2-bit (=n-n1) connection bits immediately following the n1-bit datasymbol and selected from a plurality of connection bits so that thecumulative value of DC components per unit time becomes small; and arecording portion for recording data that is output from the convertingportion on a recording medium.
 19. The recording apparatus as set forthin claim 18, wherein the converting portion is configured to select atleast one first connection bit that can be added between the immediatelypreceding data symbol and the first data symbol immediately followingthe immediately preceding data symbol, select at least one secondconnection bit that can be added between the first data symbol and thesecond data symbol, and select the first connection bit from theselected first connection bit and the second connection bit so that thecumulative value of the DC components becomes small.
 20. The recordingapparatus as set forth in claim 19, wherein the converting portion isconfigured to select the first connection bit so that when the selectedfirst connection bit and the selected second connection bit arecombined, the cumulative value of the DC components becomes small. 21.The recording apparatus as set forth in claim 18, wherein the m-bit datais modulated according to an 8-14 modulating system.
 22. The recordingapparatus as set forth in claim 18, wherein the m-bit data is modulatedaccording to an 8-16 modulating system.
 23. The recording apparatus asset forth in claim 18, wherein the converting portion is configured toselect the first connection bit when the immediately preceding datasymbol is a special data symbol.
 24. The recording apparatus as setforth in claim 23, wherein the converting portion is configured toselect the first group including at least one first connection bit thatcan be added between the immediately preceding data symbol and the firstdata symbol immediately following the preceding data symbol, select thesecond group including at least one second connection bit that can beadded between the first data symbol and the second data symbol, andselect the first connection bit from the selected first group and thesecond connection bit from the selected second group so that thecumulative value of the DC components becomes small.
 25. The recordingapparatus as set forth in claim 24, wherein the converting portion isconfigured to select the first connection bit so that when the selectedfirst connection bit and the selected second connection bit arecombined, the cumulative value of the DC components becomes small. 26.The recording apparatus as set forth in claim 23, wherein the secondconnection bit added between the first data symbol and the second datasymbol is unconditionally selected when the first data symbol isselected according to the immediately preceding data symbol and thefirst data symbol, with the special data symbol.
 27. A recording medium,comprising: a first n-bit data is selected, when m-bit data is convertedinto n-bit (where n>m) data whose run length is restricted, according toan immediately preceding n-bit data, the first n-bit data immediatelyfollowing the immediately preceding n-bit data and a second n-bit dataimmediately following the first n-bit data so that the cumulative valueof DC components per unit time becomes small and the selected firstn-bit data is recorded after the immediately preceded n-bit data,wherein the n-bit data is composed of a m-bit data symbol and n2-bit(=n-n1) connection bits immediately following the n1-bit data symbol andselected from a plurality of connection bits so that the cumulativevalue of DC components per unit time becomes small, and wherein a firstconnection bit to be added to the immediately preceding data symbol isselected according to at least one connection bit that can be addedbetween the immediately preceding data symbol and the first data symboland at least one second connection bit that can be added between thefirst data symbol and the second data symbol and recorded on therecording medium.
 28. The recording medium as set forth in claim 27,wherein a first group including at least one first connection bit thatcan be added between the immediately preceding data symbol and the firstdata symbol immediately following the immediately preceding data symbolis selected, wherein a second group including at least one secondconnection bit that can be added between the first data symbol and thesecond data symbol is selected, wherein the first connection bit isselected from the selected first group and the second connection bit isselected from the selected second group so that the cumulative value ofthe DC components becomes small, and wherein the resultantly selectedfirst connection bit is recorded on the recording medium.
 29. Therecording medium as set forth in claim 28, wherein the first connectionbit is selected so that when the selected first connection bit and theselected second connection bit are combined, the cumulative value of theDC components becomes small, and wherein the resultantly selected firstconnection bit is recorded on the recording medium.
 30. The recordingmedium as set forth in claim 27, wherein the m-bit data is modulatedaccording to an 8-14 modulating system and recorded on the recordingmedium.
 31. The recording medium as set forth in claim 27, wherein them-bit data is modulated according to an 8-16 modulating system andrecorded on the recording medium.
 32. The recording medium as set forthin claim 27, wherein the first connection bit is selected when theimmediately preceding data symbol is a special data symbol.
 33. Therecording medium as set forth in claim 32, wherein a first groupincluding at least one first connection bit that can be added betweenthe immediately preceding data symbol and the first data symbolimmediately following the immediately preceding data symbol is selected,wherein a second group including at least one second connection bit thatcan be added between the first data symbol and the second data symbol isselected, and wherein the first connection bit is selected from theselected first group and the second connection bit from the selectedsecond group so that the cumulative value of the DC components becomessmall, and wherein the resultantly selected first connection bit isrecorded on the recording medium.
 34. The recording medium as set forthin claim 33, wherein the first connection bit is selected so that whenthe selected first connection bit and the selected second connection bitare combined, the cumulative value of the DC components becomes small,and wherein the resultantly selected first connection bit is recorded onthe recording medium.
 35. The recording medium as set forth in claim 32,wherein, the second connection bit added between the first data symboland the second data symbol is unconditionally selected when the firstdata symbol is selected according to the immediately preceding datasymbol and the first data symbol, with the special data symbol.
 36. Adata converting method, comprising the step of: selecting a first n-bitdata, when m-bit data is converted into n-bit (where n>m) data whose runlength is restricted, according to an immediately preceding n-bit data,the first n-bit data immediately following the immediately precedingn-bit data and a second n-bit data immediately following the first n-bitdata so that the cumulative value of DC components per unit time becomessmall, wherein the n-bit data is composed of a m-bit data symbol andn2-bit (=n n1) connection bits immediately following the n1-bit datasymbol and selected from a plurality of connection bits so that thecumulative value of DC components per unit time becomes small; andselecting a first connection bit to be added to the immediatelypreceding data symbol according to at least one connection bit that canbe added between the immediately preceding data symbol and the firstdata symbol and at least one second connection bit that can be addedbetween the first data symbol and the second data symbol.
 37. The dataconverting method as set forth in claim 36, wherein the selecting stepcomprises the steps of: selecting a first group including at least onefirst connection bit that can be added between the immediately precedingdata symbol and the first data symbol immediately following theimmediately preceding data symbol; selecting a second group including atleast one second connection bit that can be added between the first datasymbol and the second data symbol; and selecting the first connectionbit from the selected first group the second connection bit from theselected second group so that the cumulative value of the DC componentsbecomes small.
 38. The data converting method as set forth in claim 37,wherein the first connection bit selecting step is performed byselecting the first connection bit so that when the selected firstconnection bit and the selected second connection bit are combined, thecumulative value of the DC components becomes small.
 39. The dataconverting method as set forth in claim 36, wherein the m-bit data ismodulated according to an 8-14 modulating system.
 40. The dataconverting method as set forth in claim 36, wherein the m-bit data ismodulated according to an 8-16 modulating system.
 41. The dataconverting method as set forth in claim 36, wherein the first connectionbit is selected when the immediately preceding data symbol is a specialdata symbol.
 42. The data converting method as set forth in claim 41,wherein the selecting step comprises the steps of: selecting a firstgroup including at least one first connection bit that can be addedbetween the immediately preceding data symbol and the first data symbolimmediately following the immediately preceding data symbol; selecting asecond group including at least one second connection bit that can beadded between the first data symbol and the second data symbol; andselecting the first connection bit from the selected first group and thesecond connection bit from the selected second group so that thecumulative value of the DC components becomes small.
 43. The dataconverting method as set forth in claim 42, wherein the first connectionbit selecting step is performed by selecting the first connection bit sothat when the selected first connection bit and the selected secondconnection bit are combined, the cumulative value of the DC componentsbecomes small.
 44. The data converting method as set forth in claim 41,wherein when the first data symbol is selected according to theimmediately preceding data symbol and the first data symbol, with thespecial data symbol, the second connection bit added between the firstdata symbol and the second data symbol is unconditionally selected.